The prior art diffused MOS (DMOS) field effect transistor device uses subsequent p-type and n-type diffusions through the source window in order to get a highly doped channel length L.sub.E of about 1 micrometer with the remaining portion of the channel L.sub.D being at the low doping level of the original substrate, as is illustrated in FIG. 1. FIG. 1 shows a cross-sectional view of the prior art DMOS structure, with the p-type substrate 2 having diffused into it a p-type diffusion 4 and an n-type diffusion 6 through the same window in the oxide layer 10. While the source diffusion 6 is being diffused, the n-type drain 8 is also diffused through an adjacent window in the oxide layer 10. The double diffused p-type diffusion 4 and n-type diffusion 6 form an effective channel region 20 having a length L.sub.E which is the difference between the surface of the diffusion 6 and the surface of the diffusion 4. The effective channel region 20 for the device is an enhancement mode channel. The remaining portion 22 of the region of the p-type substrate 2 between the p-type diffusion 4 and the n-type drain diffusion 8 is the depletion mode portion of the channel for the FET device. Enhancement mode channel 20 and depletion mode channel 22 are covered by a thin silicon dioxide layer 12, over which is deposited the conductive gate electrode 18, thereby forming the DMOS FET device. Electrically conductive contacts 14 and 16 are respectively deposited through windows of the oxide layer 10 to contact the source diffusion 6 and drain diffusion 8.
The fabrication process for the prior art structure of FIG. 1 borrows the hot processes used to form the p-type base and n-type emitter of bipolar transistors. Thus the problems associated with photoengraving 1 micron channel lengths are circumvented by using the more complex bipolar processing. This approach to fabricating 1 micron long channels has not been widely used to make LSI arrays primarily because of the following reasons. First, the cost-performance advantage of MOS technology is reduced by using lower manufacturing yield bipolar processing. Secondly, the threshold voltage control of the prior art device is poor because the amount of dopant deposited and redistributed during processing is not well controlled as it is in conventional MOSFET devices using uniformly doped substrates or ion-implanted channels.
It has been shown by T. J. Rogers, et al., "An Experimental and Theoretical Analysis of Double-Diffused MOS Transistors," IEEE Journal of Solid State Circuits, October 1975, pages 322-331 that if the structure of FIG. 1 is to have an effective channel length of L.sub.E approaching the length of the channel 20 for the p-type diffusion 4, the following inequality must be satisfied EQU .DELTA.V.sub.T =(V.sub.TE -V.sub.TD)&gt;1/2E.sub.c L.sub.D ( 1)
where V.sub.TE and V.sub.TD are the threshold voltages corresponding to the length of the enhancement mode channel 20 of L.sub.E and the depletion mode channel 22 length of L.sub.D, respectively, and E.sub.c is the critical electric field of 2.times.10.sup.4 volts per centimeter. For instance, if .DELTA.V.sub.T =2 volts, then L.sub.D must be less than 2 microns in order to have DMOS device characteristics. If .DELTA.V.sub.T is to be large so that it is permissible to have L.sub.D several microns long, then V.sub.TD must be made as negative as possible. One way to satisfy this requirement is to use high resistivity substrates of up to 25 ohm centimeters. However, this approach is impractical because of possible punch-through problems and it precludes having conventional MOSFETs on the same chip due to short-channel effects. Another approach may be to lower the V.sub.TD by means of ion implantation. This has the drawback, however, that such an implantation should not overlap the enhancement mode channel region 20 and consequently the alignment tolerance for the implant blocking mask must be in the micrometer range which is the kind of stringent photolithographic specification that DMOS devices were designed to avoid.